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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr st16c650a 2.90v to 5.5v uart with 32-byte fifo august 2005 rev. 5.0.1 general description the st16c650a 1 (650a) is a 2.90 to 5.5 volt universal asynchronous re ceiver and transmitter (uart) with 5 volt toler ant inputs. this device supports intel and pc isa mode data bus interfaces and is software compatible to industry standard 16c450, 16c550, and st16c580 uarts. the 650a has 32 bytes of tx and rx fifos and is capable of operating up to serial data rates of 3.125 mbps at 5 volt supply voltage. the internal registers include the 16c550 register set plus exar?s enhanced registers for additional features to support today?s highly demanding data communication needs. the enhanced features include automatic hardware and software flow control, selectable tx and rx trigger levels, and wireless infrared (irda) encoder/decoder. the device provides a new ca pability to give user the ability to program the wire less infrared encoder output pulse width, hence reducing the power consumption of a handheld unit. the st16c650a device comes in the 44-pin plcc and 48-pin tqfp packages in both the commercial and industrial temperature ranges. n ote : 1 covered by us patents #5,649,122. features added features in devices with a top mark date code of "hc yyww" and newer: 2.90 to 5.5 volt operation 5 volt tolerant inputs automatic rs485 half-d uplex control output programmable infrared encoder pulse width sleep mode with wake-up indicator device id & revision up to 3.125 mbps data rate at 5 volts added feature in devices with a top mark date code of "i2 yyww" and newer: 0 ns address hold time ? intel or pc mode 8-bit bus interface ? 32-byte transmit and receive fifos ? automatic hardware (rts/cts) flow control ? hardware flow control hysteresis ? automatic software (xon/xoff) flow control applications ? battery operated electronics ? handheld terminal ? personal digital assistants ? cellular phones dataport ? wireless infrared data communications systems f igure 1. b lock d iagram xtal1/clk xtal2 crystal osc/buffer dtr#, dsr#, rts#, cts#, cd#, ri# intel or pc data bus interface 32 byte tx fifo baud rate generator infrared encoder and pulse width control transmitter uart configuration regs ior ior# 32 byte rx fifo infrared decoder receiver with auto software flow control modem control signals tx rx cts flow control rts flow control brg prescaler cs1 cs0 ddis# int txrdy# rdrdy# a2:a0 d7:d0 iow cs2# sel s1 s2 s3 irqa irqb irqc iow# reset pc mode: com 1 to 4 decode logic
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 2 f igure 2. i ntel and pc mode p in o ut ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus st16c650acj44 44-lead plcc 0c to +70c active st16c650acq48 48-lead tqfp 0c to +70c active st16c650aij44 44-lead plcc -40c to +85c active st16c650aiq48 48-lead tqfp -40c to +85c active 44-plcc package 48-tqfp package 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 n.c. d5 d6 d7 rclk n.c. rx tx cs0 cs1 -cs2 -baudout clksel xtal1 xtal2 iow# iow gnd ior# ior n.c. as# sel reset op1# dtr# rts# op2# int rxrdy# a0 a1 a2 n.c. n.c. d4 d3 d2 d1 d0 vcc ri# cd# dsr# cts# n.c. st16c650acq48 intel bus mode (sel = vcc) ddis# txrdy# 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 n.c. d5 d6 d7 s2 a4 rx tx a5 a6 a7 lpt1# n.c. xtal1 xtal2 iow# a8 gnd ior# a3 s1 lpt2# irqc aen# sel reset op1# dtr# rts# s3 irqa irqb a0 a1 a2 n.c. n.c. d4 d3 d2 d1 d0 vcc ri# cd# dsr# cts# a9 st16c650acq48 pc mode (sel = gnd) 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 d5 d6 d7 rclk rx n.c. tx cs0 cs1 cs2# baudout# reset op1# dtr# rts# op2# sel int rxrdy# a0 a1 a2 d4 d3 d2 d1 d0 n.c. vcc ri# cd# dsr# cts# xtal1 xtal2 iow# iow gnd n.c. ior# ior ddis# txrdy# as# st16c650acj44 intel bus mode (sel = vcc) 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 d5 d6 d7 s2 rx a4 tx a5 a6 a7 lpt1# reset op1# dtr# rts# s3 sel irqa irqb a0 a1 a2 d4 d3 d2 d1 d0 a9 vcc ri# cd# dsr# cts# xtal1 xtal2 iow# a8 gnd s1 ior# a3 lpt2# irqc aen# st16c650acj44 pc mode (sel = gnd)
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 3 pin descriptions n ame 44- plcc p in # 48- tqfp p in # t ype d escription 16 (intel) mode data bus interface. the sel pin is connected to vcc. a2 a1 a0 29 30 31 26 27 28 i address bus lines [2:0] a2:a0 selects internal uart?s configuration registers. d7 d6 d5 d4 d3 d2 d1 d0 9 8 7 6 5 4 3 2 4 3 2 47 46 45 44 43 io data bus lines [7 :0] (bidirectional) ior# 24 19 i input/output read (active low) the falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [a2:a0], places it on the data bus to allow the host processor to read it on the leading edge. its function is the same as ior, except it is active low. either an active ior# or ior is required to transfer data from 650a to cpu during a read operat ion. if this input is unused, it should be connected to vcc to minimize supply current. ior 25 20 i input/output read (active high) same as ior# but active high. if this in put is unused, it should be connected to gnd to minimize supply current. iow# 20 16 i input/output write (active low) the falling edge instigates the internal write cycle and the trailing edge transfers the data byte on the data bus to an internal register pointed by the address lines [a2:a0]. its function is the sa me as iow, except it is active low. either an active iow# or iow is required to transfer data from 650a to the intel type cpu during a write operation. if this input is unused, it should be connected to vcc to minimize supply current. iow 21 17 i input/output write (active high) same as iow# but active high. if this in put is unused, it should be connected to gnd to minimize supply current. cs0 14 9 i chip select 0 input (active high) this input selects the st16c650a device. if cs1 or cs2# is used as the chip select then this pin must be connected to vcc. the 650a is selected when all three chip selects are active. see figure 3 and figure 4 . cs1 15 10 i chip select 1 input (active high) this input selects the st16c650a device. if cs0 or cs2# is used as the chip select then this pin must be connected to vcc. the 650a is selected when all three chip selects are active. see figure 3 and figure 4 . cs2# 16 11 i chip select 2 input (active low) this input selects the st16c650a device. if cs0 or cs1 is used as the chip select then this pin must be connec ted to gnd. the 650a is selected when all three chip selects are active. see figure 3 and figure 4 .
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 4 int 33 30 o interrupt output (active high) this output becomes active whenever the transmitter, receiver, line and/or modem status register has an active condition. s ee interrupt section for more details. this interrupt output may be set to normal active high or active high open source (see mcr bit-5) to provide wire-or capability by connecting a 1k to 10k ohms resistor between this pin and ground. as# 28 24 i address strobe input (active low) in the intel bus mode, the leading-edge tr ansition of as# latches the chip selects (cs0, cs1, cs2#) and the address lines a0, a1 and a2. this input is used when the address lines are not stable for the du ration of a read or write operation. in devices with top mark date code of "i2 yyww" and newer, the address bus is latched even if this input is not used. these devices feature a ?0 ns? address hold time. see ?ac electrical characteristics? . if not required, this input can be perma - nently tied to gnd. txrdy# 27 23 o uart transmitter ready (active low) the output provides the tx fifo/thr status. see table 2 . if it is not used, leave it unconnected. rxrdy# 32 29 o uart receiver ready (active low) this output provides the rx fifo/rhr status for receive channel a. see table 2 . if it is not used, leave it unconnected. pc mode interface signals. connect sel pin to gnd to select pc mode. a3 a4 a5 a6 a7 a8 a9 25 12 14 15 16 21 1 20 6 9 10 11 17 37 i pc mode additional address lines in the pc mode, these are the additional address lines from the host address bus. they are inputs to the on-board chip sele ct decode function for com 1-4 and lpt ports. see table 1 for details. the pins a4 and a9 have internal 100k ? pull-up resistors. aen# 28 24 i address enable input (active low) when aen# transition to logic 0, it decodes and validates com 1-4 ports address per s1, s2 and s3 inputs. s1 s2 s3 23 10 35 21 5 31 i select 1 to 3 these are the standard pc com 1-4 ports and irq selection inputs. see table 1 and table 3 for details. the s1 pin has an internal 100k ? pull-up resistor. irqa irqb irqc 33 32 27 30 29 23 o interrupt request a, b and c outputs (active high, tri-state) these are the interrupt outputs associated with com 1-4 to be connected to the host data bus. see interrupt section for de tails. the interrupt requests a, b or c functions as irqx to the pc bus. irqx is enabled by setting mcr bit-3 to logic 1 and the desired interrupt(s) in the interrupt enable register (ier). lpt1# 17 12 o line printer port-1 decode logic output (active low) this pin functions as the pc standard lpt-1 printer port address decode logic out - put, see table 1 . the baud rate generator clock output, baudout#, is internally connected to the rclk input in the pc mode. n ame 44- plcc p in # 48- tqfp p in # t ype d escription
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 5 lpt2# 26 22 o line printer port-2 decode logic output (active low) this pin functions as the pc standard lpt-2 printer port address decode logic out - put, see table 1 . modem or serial i/o interface tx 13 8 o transmit data or wireless infrared transmit data this output is active low in normal stand ard serial interface operation (rs-232, rs-422 or rs-485) and active high in the infrared mode. rx 11 7 i receive data or wireless infrared receive data normal received data input idles at logic 1 condition and logic 0 in the infrared mode. the wireless infrared pulses are applie d to the decoder. this input must be connected to its idle logic state in either normal, logic 1, or infrared mode, logic 0, else the receiver may report ?rece ive break? and/or ?error? condition(s). rts# 36 32 o request to send or general purpose output (active low) this port may be used for one of two functions: 1) automatic hardware flow control, see efr bit-6, mcr bit-1and ier bit-6. 2) rs485 half-duplex direction co ntrol, see xfr bits 2 and 5. rts# output must be asserted before auto rts flow control can start. cts# 40 38 i clear to send or general purpose input (active low) if used for automatic hardware flow c ontrol, data transmission will be stopped when this pin is de-asserted and will resu me when this pin is asserted again. see efr bit-7 and ier bit-7. dtr# 37 33 o data terminal ready or general purpose output (active low) dsr# 41 39 i data set ready input or general purpose input (active low) cd# 42 40 i carrier detect input or general purpose input (active low) ri# 43 41 i ring indicator input or general purpose input (active low) ancillary signals xtal1 18 14 i crystal or external clock input. caut ion: this input is not 5v tolerant. xtal2 19 15 o crystal or buffered clock output rclk 10 5 i receiver clock this input is used as external 16x clock i nput to the receiver section. connect the baudout# pin to this input externally. baudout# 17 12 o baud rate generator output (active low) this pin provides the 16x clock of the selected data rate from the baud rate gener - ator. the rclk pin must be connect ed externally to baudout# when the receiver is operating at the same data rate. when the pc mode is selected, the baud ra te generator clock output is internally connected to the rclk input. this pin then functions as the lpt-1 printer port decode logic output, see table 3 . sel 34 36 i pc mode select (active low) when this input is at logic 0, it enables the on-board chip select decode function according to pc isa bus com[4:1] and irq[4:3] port definitions. see table 3 for details. this pin has an internal 100k ? pull-up resistor. n ame 44- plcc p in # 48- tqfp p in # t ype d escription
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 6 pin type: i=input, o=output, io= i nput/output, od=output open drain. ddis# 26 22 o drive disable output this pin goes to a logic 0 whenever the ho st cpu is reading data from the 650a. it can control the direction of a data bus transceiver between the cpu and 650a or other logic functions. reset 39 35 i reset input (active high) a 40 ns minimum active pulse on this pin will reset the internal registers and all outputs. the uart transmitter output will be held at logic 1, the receiver input will be ignored and outputs are reset. see uart reset conditions in table 13 . op1# 38 34 o output port 1 general purpose output. op2# 35 31 o output port 2 general purpose output. vcc 44 42 pwr 2.90v to 5.5v supply voltage all inputs are 5v tolerant except for xtal for devices with date code top mark of "hc yyww" and newer. devices with date code top mark of "gc yyww" and older do not have 5v tolerant inputs. gnd 22 18 pwr power supply common ground nc - 1, 13, 25 - no connect n ame 44- plcc p in # 48- tqfp p in # t ype d escription
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 7 1.0 product description the st16c650a (650a) is a low power uart that can operate from 2.90v to 5.5v power supplies. its inputs are 5v tolerant to facilitate intercon nection to transceiver devices of rs-2 32, rs-422 or rs-485. the 650a is software compatible to the in dustry standard 16c550 with some additional enhanced features. the 650a provides serial asynchronous receive data syn chronization, parallel-to-serial data conversion for the transmitter section and serial-to-parallel data conversion s for receiver section. these functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. synchronization for the serial data stream is accomplish ed by adding start and stop bits to the transmitted data to form a data character (character orientated protocol). da ta integrity is ensured by attaching a parity bit to the data character. the parity bit is checked by the receiver for any transmission bit errors. the electronic circuitry to provide all these functions is fair ly complex especially when manufactur ed on a single in tegrated silicon chip. the st16c650a represents such an integration wit h greatly enhanced features. the 650a is fabricated with an advanced cmos process. the 650a supports standard 8-bit intel or pc bus interf aces through an input selection pin (sel input pin). the intel bus uses the standard read and write signals for all bus transactions. the pc bus mode associates with the pc isa bus and follow the industry standard pc defi nitions for com 1-4 serial port addresses. the 650a includes on-board chip select decode logic and selection for the proper interrupt request. this eliminates the need for an external logic array device. the 650a has 32-bytes each of transmit and receive fifos, automatic rts/cts ha rdware flow control with hysteresis, automatic xon/xoff and special character so ftware flow control, sele ctable transmit and receive fifo trigger levels, wireless infrared encoder and decod er (irda ver. 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rates up to 3.125 mbps with a 16x sampling clock rate. the 650a is an upward solution that provides 32 byte s of transmit and receive fifo memory, instead of 16 bytes provided in the 16c550, or none in the 16c4 50. the 650a is designed to work with high speed communication devices, that require fast data processing time. increased performance is realized in the 650a by the larger transmit and receive fifos. this allows the external processor to handle more networking tasks within a given time. for example, the standard st16c550 with a 16 byte fifo, unloads 16 bytes of receive data in 1.53 ms (this example uses a character length of 11 bits, including start/stop bits at 115.2kbps). this means the external cpu will have to service the receive fifo at 1.53 ms intervals. however with the 32 byte fifo in the 650a, the data buffer will not require unloading/lo ading for 3.05 ms. this increases the service interval giving the external cpu additional time for ot her applications and reducing the overall uart interrupt servicing time. in addition, the 4 selectable levels of fifo trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data throughput performance especially when operating in a multi-channel environment. the combination of the abov e greatly reduces the band width requirement of the external controlling cpu, in creases performance, and re duces power consumption. the rich feature set of the 650a is available through internal registers. automa tic hardware/software flow control, selectable transmit and receive fifo trigger levels, selectable tx and rx baud rates, infrared encoder/decoder interface, modem inte rface controls, and a sleep mode are all standard features. in the pc mode, two tri-state interrupt lines (irqb and irqc) and one selectable open source interrupt output (irqa) are available. the open source interrupt scheme allows multiple interrupts to be combined in a ?wire-or? operation, thus reducing the number of interrupt lines in larger systems. following a power on reset or an external reset, the 650a is softwa re compatible with previous generation of uarts, 16c450, 16c550 and st16c580.
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 8 2.0 functional descriptions 2.1 host data bus interface the host interface is 8 data bits wide with 3 address li nes and control signals to execute bus read and write transactions. the 650a supports 2 type of host interf aces: intel and pc mode. th e intel bus interface is selected by connecting sel to a logic 1. th e intel bus interconnections are shown in figure 3 . the special pc mode is selected when sel is connected to a logi c 0. the pc mode interconnections are shown in figure 4 . f igure 3. st16c650a i ntel b us i nterconnections f igure 4. st16c650a pc m ode i nterconnections d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 ior* iow* reset d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# a0 a1 a2 cs2# reset vcc cs0 cs1 as# ior iow int int rclk baudout# sel vcc gnd cs# op2# op1# dsr# cts# rts# dtr# rx tx ri# cd# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 a7 a14 a15 aen# iow# ior# reset d0 d1 d2 d3 d4 d5 d6 d7 iow# a0 a1 a2 reset vcc cs0 cs1 as# ior iow irqn irqa sel vcc gnd ior# irqb irqc irq4 irq3 a3 a4 a5 a6 a7 a8 a9 aen* op1# ri# cd# dsr# cts# rx tx rts# dtr# s1 s2 s3 vcc gnd gnd
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 9 2.1.1 pc mode the pc mode interface includes an on-chip address deco der and interrupt selection function for the standard pc com 1-4 port addresses. the selection is made thro ugh three input signals: s1, s2 and s3. the selection summary is shown in table 1 . although the on-chip address decoder was designed for pc applications ranging from 0x278 to 0x3ff, it can fit into an embedde d applications by offsetting the address lines to the 650a. an example is shown in figure 5 where the uart is operating from 0x80f8 to 0x80ff address space. operating in the pc mode eliminates external address decode components. t able 1: pc m ode i nterface o n - chip a ddress d ecoder and i nterrupt s election . sel input s3, s2, s1 i nputs a9-a3 a ddress l ines to o n - chip d ecoder com/lpt p ort s election irq o utput s election 0 0 0 0 0x3f8 - 0x3ff com-1 irqb (for pc?s irq4) 0 0 0 1 0x2f8 - 0x2ff com-2 irqc (for pc?s irq3) 0 0 1 0 0x3e8 - 0x3ef com-3 irqb (for pc?s irq4) 0 0 0 0 0x3f8 - 0x3ff com-4 irqb (for pc?s irq4) 0 1 0 0 0x2f8 - 0x2ff com-1 irqa (for pc?s irqn 0 1 0 1 0x3e8 - 0x3ef com-2 irqa (for pc?s irqn) 0 1 1 0 0x2e8 - 0x2ef com-3 irqa (for pc?s irqn) 0 1 1 1 0x3f8 - 0x3ff com-4 irqa (for pc?s irqn) 0 - - - 0x278 - 0x27f lpt-2 n/a 0 - - - 0x378 - 0x37f lpt-1 n/a f igure 5. pc m ode i nterface in an e mbedded a pplication . d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 a7 a14 a15 aen# iow # ior# reset d0 d1 d2 d3 d4 d5 d6 d7 io w # a0 a1 a2 reset vcc int irqa sel vcc gnd io r# irqb irqc a3 a4 a5 a6 a7 a8 a9 aen* op1# ri# cd# dsr# cts# rx tx rts# dtr# s1 s2 s3 vcc gnd gnd embedded application set to operate at address 0x80f8 to 0x80ff
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 10 2.2 5-volt tolerant inputs the 650a can acccept up to 5v inputs even when operat ing at 3.3v. caution: xtal1 is not 5 volt tolerant. 2.3 device reset the reset input resets the internal registers and the serial interface ou tputs to their default state (see figure 13 ). an active high pulse of longer than 40 ns duration will be requ ired to activate the reset function in the device. 2.4 device identification and revision the st16c650a provides a device identification code and a device revision code to distinguish the part from other devices and revisions. to read the identification code from the part, it is required to set the baud rate generator regist ers dll and dlm both to 0x00. now reading the content of th e dlm will provide 0x04 for the st16c650a and reading the cont ent of dll will provide the revision of th e part; for example, a reading of 0x01 means revision a. 2.5 dma mode the device does not support direct memory access. th e dma mode (a legacy term) in this document does not mean ?direct memory access? but refers to data block transfer operation. the dma mode affects the state of the rxrdy# and txrdy# output pins. the transmit an d receive fifo trigger levels provide additional flexibility to the user for block mode operation. the lsr bits 5- 6 provide an indication when the transmitter is empty or has an empty location(s) for more data. the user can optionally operate the transmit and receive fifo in the dma mode (fcr bit-3=1). when the transmit and receive fifo are enabled and the dma mode is disabled (fcr bit-3 = 0), the 650a is placed in single- character mode for data transmit or receive operation. when dma mode is enabled (fcr bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the fifo in a block sequence determined by the programmed trigger level. in this mode, the 650a sets the txrdy# pin when the transmit fifo becomes fu ll, and sets the rxrdy# pin when the receive fifo becomes empty. the following table shows their behavior. also see figures 23 through 28 . t able 2: txrdy# and rxrdy# o utputs in fifo and dma m ode p ins fcr bit -0=0 (fifo d isabled ) fcr b it -0=1 (fifo e nabled ) fcr b it -3 = 0 (dma m ode d isabled ) fcr b it -3 = 1 (dma m ode e nabled ) rxrdy# 0 = 1 byte. 1 = no data. 0 = at least 1 byte in fifo 1 = fifo empty. 1 to 0 transition when fifo reaches the trigger level, or timeout occurs. 0 to 1 transition when fifo empties. txrdy# 0 = thr empty. 1 = byte in thr. 0 = fifo empty. 1 = at least 1 byte in fifo. 0 = fifo has at least 1 empty location. 1 = fifo is full.
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 11 2.6 interrupt the output function of interrupt, int, output changes ac cording to the operating bus type and various factors. table 3 summarizes its behavior in intel and pc mode of op eration. multiple interrupt s can be wire-or?ed. this is accomplished by setting mcr bit-5 to a logic 1 and connecting a 1k ? to 10k ? resistor between this pin and ground to provide an acceptable logic 0 level. t able 3: i nterrupt o utput (int and irqa) f unctions sel i nput s3 i nput mcr bit -5 (int type select ) mcr bit -3 (irq n enable ) i nterrupt o utput (int or irqa) intel bus mode 1 don?t care 0 don?t care int is logic 0 for inactive interrupt. int is logic 1 for active interrupt (active high) 1 don?t care 1 don?t care int is three-state fo r inactive interrupt int is logic 1 for active interrupt (open source). requires a 1k- 10k ? resistor to gnd. pc mode 0 0 don?t care don?t care irqa is three-state. either irqb or irqc is used, see table 1 . 0 1 don?t care 0 irqa is three-state. 0 1 0 1 irqa is logic 0 for inactive interrupt. irqa is logic 1 for active interrupt (active high). 0 1 1 1 irqa is three-state for no interrupt. irqa is logic 1 for active interrupt (active high, open source).
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 12 2.7 crystal oscillator or external clock the 650a includes an on-chip oscilla tor (xtal1 and xtal2). the crystal os cillator provides the system clock to the baud rate generators (brg) in the uart. xtal1 is the input to the oscillator or ex ternal clock buffer input with xtal2 pin being the output. caution if external clock is used: xtal1 input is not 5 volt tolerant. for programming details, see ?programmable baud rate generator.? the on-chip oscillator is designed to use an industry standard micropro cessor crystal (p arallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-120 ohms and 100 ppm frequency tolerance) connected externally between the xtal1 and xtal2 pins (see figure 6 ). alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for standard or custom rates. typically, the oscillator connections are shown in figure 6 . for further reading on os cillator circuit please see application note dan108 on exar?s web site. 2.8 programmable baud rate generator the uart has its own baud rate ge nerator (brg) with a prescaler for th e transmitter. the prescaler is controlled by a software bit in the mcr register. the mcr register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. the clock output of the prescaler goes to the brg. the brg further divides this clock by a programmable divisor between 1 and (2 16 -1) to obtain a 16x sampling clock of the serial data rate. the sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. the brg divisor (dll and dlm registers) defaults to a random value upon power up or a reset. therefore, the brg must be programmed during initialization to the operating data rate. f igure 6. t ypical oscillator connections c1 22-47 pf c2 22-47 pf y1 1.8432 mhz to 24 mhz r1 0-120 ? (optional) r2 500 ? ? 1 ? xtal1 xtal2
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 13 programming the ba ud rate generator regi sters dlm and dll provides th e capability of selecting the operating data rate. table 4 shows the standard data rates availabl e with a 14.7456 mhz crystal or external clock at 16x clock rate. when using a non-standard data rate crystal or external clock, the divisor value can be calculated for dll/dlm wit h the following equation. 2.9 transmitter the transmitter section comprises of an 8-bit transmit shift register (tsr) and 32 bytes of fifo which includes a byte-wide transmit holding register (thr). tsr shifts out every data bit with the 16x internal clock. a bit time is 16 clock periods. the transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop -bit(s). the status of the fifo and tsr are reported in the line status register (lsr bit-5 and bit-6). f igure 7. b aud r ate g enerator divisor (decimal) = (xtal1 clock frequency / prescaler) / (serial data rate x 16) t able 4: t ypical data rates with a 14.7456 mh z crystal or external clock o utput data rate mcr bit-7=1 o utput data rate mcr bit-7=0 d ivisor for 16x clock (decimal) d ivisor for 16x clock (hex) dlm p rogram v alue (hex) dll p rogram v alue (hex) d ata r ate e rror (%) 100 400 2304 900 09 00 0 600 2400 384 180 01 80 0 1200 4800 192 c0 00 c0 0 2400 9600 96 60 00 60 0 4800 19.2k 48 30 00 30 0 9600 38.4k 24 18 00 18 0 19.2k 76.8k 12 0c 00 0c 0 38.4k 153.6k 6 06 00 06 0 57.6k 230.4k 4 04 00 04 0 115.2k 460.8k 2 02 00 02 0 230.4k 921.6k 1 01 00 01 0 xtal1 xtal2 crystal osc/ buffer mcr bit-7=0 (default) mcr bit-7=1 dll and dlm registers prescaler divide by 1 prescaler divide by 4 16x sampling rate clock to transmitter baud rate generator logic
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 14 2.9.1 transmit holding regi ster (thr) - write only the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted into a serial data stream including a start bit, data bits, parity bit and stop bit(s). the least-significant-bit (bit-0 ) is the first data bit to go out. the thr is the input register to the transmit fifo of 32 bytes when fifo operation is enabl ed by fcr bit-0. every time a write operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential data location. 2.9.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a tr ansmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr beco mes completely empty. 2.9.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 32 bytes of transmit data. t he thr empty flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can ge nerate a transmit empty interrupt (isr bit-1) when the amount of data in the fifo falls below its programmed tr igger level. the transmit em pty interrupt is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr/fifo becomes empty. f igure 8. t ransmitter o peration in non -fifo m ode f igure 9. t ransmitter o peration in fifo and f low c ontrol m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x clock transmit data shift register (tsr) transmit data byte thr interrupt (isr bit-1) falls below the programmed trigger level and then when becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo 16x clock auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg. txfifo1
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 15 2.10 receiver the receiver section contains an 8-bit receive shift register (rsr) and 32 bytes of fifo which includes a byte-wide receive holding register (rhr). the rsr uses the 16x clock for timing. it verifies and validates every bit on the incoming char acter in the middle of each data bit. on the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16x clock rate. after 8 clocks the start bit period should be at the center of the start bit. at this time the start bit is sa mpled and if it is still a logic 0 it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if there were any error(s), they are reported in the lsr register bits 2-4. upon unloading the receive data byte from rhr, the receive fifo pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in the rhr register. rhr can generate a receive data ready interrupt upon receiving a character or delay until it reaches the fifo trigger leve l (xfr bit-3). furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not re ceived for 4 word lengths as defined by lcr[1:0] plus 12 bits time. this is equivalent to 3.7-4.6 character times. the rhr interrupt is enabled by ier bit-0. 2.10.1 receive holding register (rhr) - read-only the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register. it provides the receive data interface to the host processor. the rhr register is part of the receive fifo of 32 bytes by 11-bits wide, the 3 extra bits are fo r the 3 error tags to be reported in lsr register. when the fifo is enabled by fcr bit-0, the rhr contains th e first data character received by the fifo. after the rhr is read, the next character byte is loaded into the rhr and the errors associated with the current data byte are immediately updated in the lsr bits 2-4. f igure 10. r eceiver o peration in non -fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x clock receive data characters data bit validation error tags in lsr bits 4:2
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 16 2.11 automatic rts (hardware) flow control automatic rts hardware flow control is used to prevent data overrun to the local receiver fifo. the rts# output is used to request remote unit to suspend/r esume data transmission. the auto rts flow control features is enabled to fit specific application requirement (see figure 12 ): ? enable auto rts flow control using efr bit-6. ? the auto rts function must be started by asserting rts output pin (mcr bit-1 to logic 1 after it is enabled). with the auto rts function enabled, the rts# output pin will no t be de-asserted (logic 1) when the receive fifo reaches the progr ammed trigger level, but will be de-asserted when the fifo reaches the next trigger level ( see table 10 ). the rts# output pin will be a sserted again after the fifo is unloaded to th e next trigger level below the programmed tr igger level. however, even under thes e conditions, the 650a will continue to accept data until the receive fifo is full if the remote uart tr ansmitter continues to send data. ? enable rts interrupt through ier bit-6 (after setting efr bit-4). the uart issues an interrupt when the rts# pin is de-asserted (logic 1) during auto rts flow control mode: isr bit-5 will be set to logic 1. 2.12 auto cts flow control automatic cts flow control is used to prevent data overrun to the remote receiver fifo. the cts# input is monitored to suspend/restart the local transmitter. the aut o cts flow control feature is selected to fit specific application requirement (see figure 12 ): ? enable auto cts flow control using efr bit-7. with the auto cts function enabled, the uart will suspend transmission as soon as the stop bit of the character in the transmit shift register has been shifted out. transmission is resumed after the cts# input is re-asserted (logic 0), indicating more data may be sent. ? enable cts interrupt through ier bit-7 (after setting efr bit-4). the uart issues an interrupt when the cts# pin is de-asserted (logic 1) during auto cts flow control mode: isr bit-5 will be set to 1. f igure 11. r eceiver o peration in fifo and a uto rts f low c ontrol m ode receive data shift register (rsr) rxfifo1 16x clock error tags (32-sets) error tags in lsr bits 4:2 32 bytes by 11-bit wide fifo receive data characters fifo trigger=16 example : - rx fifo trigger level selected at 16 bytes data fills to 24 data falls to 8 data bit validation receive data fifo receive data receive data byte and errors rhr interrupt (isr bit-2) programmed for desired fifo trigger level. fifo is enabled by fcr bit-0=1 rts# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-1. rts# re-asserts when data falls below the flow control trigger level to restart remote transmitter. enable by efr bit-6=1, mcr bit-1.
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 17 2.13 auto xon/xoff (software) flow control when software flow control is enabled ( see table 12 ), the 650a compares one or two sequential receive data characters with the programmed xon or xoff-1,2 charac ter value(s). if received ch aracter(s) (rx) match the programmed values, the 650a will halt tr ansmission (tx) as soon as th e current character has completed transmission. when a match occurs, the xoff (if enabled vi a ier bit-5) flag will be set and the interrupt output pin will be activated. followi ng a suspension due to a ma tch of the xoff character values, the 650a will monitor the receive data stream for a match to the xon-1,2 ch aracter value(s) . if a match is found, the 650a will resume operation and clear the flags (isr bit-4). reset initially sets the contents of the xon/xoff 8-bit flow control registers to a logic 0. following reset the user can write any xon/xoff value desired for software flow c ontrol. different conditions can be set to detect xon/ xoff characters ( see table 12 ) and suspend/resume transmissions. when double 8-bit xon/xoff characters are selected, the 650a compares two consecutive rece ive characters with two software flow control 8-bit values (xon1, xon2, xoff1, xoff2) and controls tx tran smissions accordingly. under the above described flow f igure 12. a uto rts and cts f low c ontrol o peration the local uart (uarta) starts data transfer by asserting rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to se nd data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger le vel, uarta activates its rxa data ready interrupt (5) and con - tinues to receive and put data into its fifo. if interrupt se rvice latency is long and data is not being unloaded, uarta monitors its receive data fill level to match the upper thre shold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. ua rtb stops or finishes sending the data bits in its trans - mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow. rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 18 control mechanisms, flow control charac ters are not placed (stacked) in the user accessible rx data buffer or fifo. in the event that the receive buffer is overfilling and flow control needs to be executed, the 65 0a automatically sends an xoff message (when enabled) via the serial tx output to the remote modem. the 650a sends the xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate) after the receive fifo crosses the pr ogrammed trigger level. to clear this condition, the 650a will transmit the programmed xon-1,2 characters as soon as receive fifo drops to one trigger level below the programmed trigger level. table 5 below explains this: * after the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2 characters); for example, after 2.083ms has el apsed for 9600 baud and 10-bit word length setting. 2.14 special character detect a special character detect feature is provided to detect an 8-bit character when bit-5 is set in the enhanced feature register (efr). when this character (xoff2) is detected, it will be placed in the fi fo along with normal incoming rx data. the 650a compares each incoming receiv e character with xoff-2 data. if a match exists, the received data will be transferred to the rx fifo and isr bit-4 will be set to indica te detection of a special character. although the internal register table shows each x-register with eight bits of character information, the actual number of bits is dependent on the programmed word leng th. line control register (lcr) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bi ts, or 8 bits. the word length selected by lcr bits 0-1 also determines the number of bits that will be used for the special ch aracter comparison. bit-0 in the x- registers corresponds with the l sb bit for the receive character. 2.15 auto rs485 half-duplex control the auto rs485 half-duplex direction control changes the behavior of the transmitter when enabled by xfr bit-3. by default, it asserts rts# (logic 0) output following the last stop bit of the last character that has been transmitted. this helps in turning around the transceiver to receive the remote station?s response. when the host is ready to transmit next polling data packet again, it only has to load data bytes to the transmit fifo. the transmitter automatically re-asserts rts# (logic 1) ou tput prior to sending the data. the rs485 half-duplex direction control output polarity can be inverted by enabling xfr bit-5. t able 5: a uto x on /x off (s oftware ) f low c ontrol rx t rigger l evel int p in a ctivation x off c haracter ( s ) s ent ( characters in rx fifo ) x on c haracter ( s ) s ent ( characters in rx fifo ) 8 8 8* 0 16 16 16* 8 24 24 24* 16 28 28 28* 24 t able 6: rs485 h alf -d uplex c ontrol xfr b it -2 xfr b it -5 rts# p in 0 x rs485 half-duplex control disabled 1 0 logic 1 = tx logic 0 = rx 1 1 logic 1 = rx logic 0 = tx
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 19 2.16 infrared mode the 650a uart includes the infrared encoder and decoder compatible to the irda (infrared data association) version 1.0. the infrared mode can be enabled by setting m cr bit-6 to a ?1?. in the infrared mode, the user can choose to send/receive data either half-duplex or full-du plex. the half-duplex mode is chosen by setting bit-0 of xfr register to a ?1?. this prevents echoed data from reaching the receiver. when the infrared feature is enabled, the transmit data outputs, tx, idles at logic zero level. likewise, the rx input assumes an idle level of logic zero, see figure 13 . the irda standard defines the infrared encoder sends out a 3/16 of a bit wide high-pulse for each ?0? bit in the transmit data stream. this signal encoding reduces the on -time of the infrared led, hence reduces the power consumption. see figure 13 below. the 650a has an additional feature to allow user to vary the transmit pulse width further reducing power consumpt ion of the system where application permits (see irpw register for details). the wireless infrared decoder receives the input pulse from the infrared sensing diode on rx pin. each time it senses a light pulse, it returns a logic 0 to the data bit stream. the 650a also includes another feature - inversion of the ir pulse (xfr register bit-1), where a low ir pulse in the receive data stream is recognized as a ?0? bit. f igure 13. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder - rx data receive ir pulse (rx pin) character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 bit time irencoder-1
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 20 2.17 sleep mode & wake-up indicator the 650a is designed to operate with low power cons umption. a special sleep mode is included to further reduce power consumption when the chip is not being us ed. all of these conditions must be satisfied for the 650a to enter sleep mode: no interrupts pending 650a (isr bit-0 = 1) sleep mode is enabled (ier bit-4 = 1) modem inputs are not toggling (msr bits 0-3 = 0) rx input pin is idling at a logic 1 the 650a stops its crystal oscillator to conserve power in the sleep mode. user can check the xtal2 pin for no clock output as an indication that the device has entered the sleep mode. the 650a resumes normal operation by any of the following: a receive data start bit transition (logic 1 to 0) a data byte is loaded to the transmitter, thr or fifo a change of logic state on any of the modem or general purpose serial inputs: cts#, dsr#, cd#, ri# if the sleep mode is enabled and the 650a is awakened by one of the conditions described above, an interrupt is issued by the 650a to signal to the cpu that it is awake. the lower nibble of th e interrupt source register (isr) will read a value of 0x1 for this interrupt and re ading the isr clears this interrupt. since the same value (0x1) is also used to indicate no pending interrupt, users should exercise caution while using the sleep mode. once awakened, the 650a will return to the sleep mode au tomatically after any other interrupting condition (the true cause of waking up the 650a) has been serviced. if the 650a is awakened by the modem inputs, a read to the msr is required to re set the modem inputs. in any case, the sleep mode will not be entered while an interrupt is pending. the 650a will stay in the sleep mode of oper ation until it is disabled by setting ier bit-4 to a logic 0.
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 21 2.18 internal loopback the 650a uart provides an internal loopback capability for system diagnostic purposes . the internal loopback mode is enabled by setting mcr register bit-4 to logi c 1. all regular uart functions operate normally. figure 14 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to re ceive the same data that it was sending. the tx pin is held at logic 1 or mark condition while rts# and dtr# are de-asserted, and cts#, dsr# cd# and ri# inputs are igno red. caution: the rx input must be held to a logic 1 during loopback test else upon exiting the loopback test the uart may detect and report a false ?break? signal. also, auto rts/cts is not supported during internal loopback. f igure 14. i nternal l oop b ack tx rx modem / general purpose control logic internal data bus lines and control signals rts# mcr bit-4=1 vcc vcc transmit shift register (thr/fifo) receive shift register (rhr/fifo) cts# dtr# dsr# ri# cd# op1# op2# rts# cts# dtr# dsr# ri# cd# vcc vcc op2# vcc op1#
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 22 3.0 uart configuration registers the 650a has a set of configuration registers selected by address lines a0 to a2. the based page registers are 16c550 compatible with exar enhanced feature register s located on the second page (mirror) addresses. the second page registers are only accessible by setting lcr register to a value of 0xbf. the register set is shown on table 7 and table 8 . . t able 7: st16c650a uart configuration registers a ddress r egister r ead /w rite c omments a2 a1 a0 16550 c ompatible r egisters 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 dll - divisor latch low read/write lcr[7] = 1, lcr 0xbf 0 0 1 dlm - divisor latch high read/write lcr[7] = 1, lcr 0xbf 0 0 0 drev - device revision code read-only lcr[7] = 1, lcr 0xbf, dll, dlm = 0x00 0 0 1 dvid - device identification code read-only lcr[7] = 1, lcr 0xbf, dll, dlm = 0x00 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 1 0 isr - interrupt status register fcr - fifo control register read-only write-only lcr[7] = 0 0 1 1 lcr - line control register read/write 1 0 0 mcr - modem control register read/write lcr[7] = 0 1 0 1 lsr - line status register read-only lcr[7] = 0 xfr - extra feature register write-only lcr[7] = 0, efr[4] = 1 1 1 0 msr - modem status register read-only lcr[7] = 0 irpw - infrared pulse width register write-only lcr[7] = 0, efr[4] = 1 1 1 1 spr - scratch pad register read/write lcr[7] = 0 e nhanced r egisters 0 1 0 efr - enhanced function register read/write lcr = 0xbf 1 0 0 xon-1 - xon character 1 read/write lcr = 0xbf 1 0 1 xon-2 - xon character 2 read/write lcr = 0xbf 1 1 0 xoff-1 - xoff character 1 read/write lcr = 0xbf 1 1 1 xoff-2 - xoff character 2 read/write lcr = 0xbf
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 23 t able 8: uart configuratio n registers description. s haded bits are enabled when efr b it -4=1. a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0 0 0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 0 0 0 0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier rd/wr 0/ 0/ 0/ 0/ modem stat. int. enable rx line stat. int. enable tx empty int enable rx data int. enable cts int. enable rts int. enable xoff int. enable sleep mode enable 0 1 0 isr rd fifos enabled fifos enabled 0/ 0/ int source bit-3 int source bit-2 int source bit-1 int source bit-0 int source bit-5 int source bit-4 0 1 0 fcr wr rx fifo trigger rx fifo trigger 0/ 0/ dma mode enable tx fifo reset rx fifo reset fifos enable tx fifo trigger tx fifo trigger 0 1 1 lcr rd/wr divisor enable set tx break set par - ity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 mcr rd/wr 0/ 0/ 0/ internal loop - back enable op2#/ irqn output enable op1# rts# output control dtr# output control lcr[7]=0 brg pres - caler ir mode enable int type select 1 0 1 lsr rd rx fifo error tsr empty thr empty rx break rx fram - ing error rx parity error rx data over - run error rx data ready xfr wr rsrvd rsrvd invert rs485 control output enable xonany lsr int mode auto rs485 enable invert ir rx input enable half- duplex ir 1 1 0 msr rd cd ri dsr cts delta cd# delta ri# delta dsr# delta cts# irpw wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 24 4.0 internal register descriptions 4.1 receive holding register (rhr) - read-only see?receiver? on page 15. 4.2 transmit holding register (thr) - write-only see?transmitter? on page 13. 4.3 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are report ed in the interrupt status register (isr) register. 4.3.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = a logic 1) and receive interrupts (ier bit-0 = logic 1) are enabled, the rhr interrupts (see isr bits 2 and 3) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared wh en the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty. baud rate generator divisor 0 0 0 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 lcr 0xbf 0 0 1 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 drev rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 1 lcr 0xbf dll=0x00 dlm=0x00 0 0 1 dvid rd 0 0 0 0 0 1 0 0 enhanced registers 0 1 0 efr r/w auto cts enable auto rts enable special char select enable ier [7:4], isr [5:4], fcr[5:4], mcr[7:5] msr[7:4] irpw[7:0] xfr[7:0] soft - ware flow cntl bit-3 soft - ware flow cntl bit-2 soft - ware flow cntl bit-1 soft - ware flow cntl bit-0 lcr=0xbf 1 0 0 xon1 r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 xon2 r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 0 xoff1 r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 xoff2 r/w bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 t able 8: uart configuratio n registers description. s haded bits are enabled when efr b it -4=1. a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 25 4.3.2 ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1 for fifo enable; resett ing ier bits 0-3 enables the st16c650a in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bits 2-4 provides the type of receive data erro rs encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data characte r in the non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. ? logic 0 = disable the receive data ready interrupt (default). ? logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit ready interrupt which is issued whenever the thr becomes empty in the non- fifo mode or when data in the fifo fa lls below the programmed trigger level in the fifo mode. if the thr is empty when this bit is enabled , an interrupt will be generated. ? logic 0 = disable transmit holding re gister empty interrupt (default). ? logic 1 = enable transmit holding register empty interrupt. ier[2]: receive line status interrupt enable any change of state of the lsr register bits 1, 2, 3 or 4 will generate an interrupt to inform the ho st controller about the error status of the current data byte in fifo. lsr bit-1 generates an interrupt immediately when the character has been received. lsr bits 2-4 generate an interrupt either when the character with errors is next to be read out of the fifo (xfr[3] = 0) or when the received chracter is received (xfr[3] = 1). ? logic 0 = disable the receiver line status interrupt (default). ? logic 1 = enable the receiver line status interrupt. ier[3]: modem status interrupt enable ? logic 0 = disable the modem status register interrupt (default). ? logic 1 = enable the modem status register interrupt. ier[4]: sleep mode enable (requires efr bit-4 = 1) ? logic 0 = disable sleep mode (default). ? logic 1 = enable sleep mode. see?sleep mode & wake-up indicator? on page 20. ier[5]: xoff interrupt enable (requires efr bit-4=1) ? logic 0 = disable the software flow cont rol, receive xoff interrupt (default). ? logic 1 = enable the software flow control, receive xoff interrupt. see?auto xon/xoff (software) flow control? on page 17. ier[6]: rts# output interrupt enable (requires efr bit-4=1) ? logic 0 = disable the rts# interrupt (default). ? logic 1 = enable the rts# interrupt. the uart issues an interrupt when the rts# pin makes a transition from low to high.
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 26 ier[7]: cts# input interrupt enable (requires efr bit-4=1) ? logic 0 = disable the cts# interrupt (default). ? logic 1 = enable the cts# interrupt. the uart issues an interrupt when cts# pin makes a transition from low to high. 4.4 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current highe st pending interrupt level to be serviced, others queue up for next service. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source ta b l e , table 9 , shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. 4.4.1 interrupt generation: ? lsr is by any of the lsr bits 1, 2, 3 and 4. ? rxrdy is by rx trigger level. ? rxrdy time-out is by a 4-char plus 12 bits delay timer. ? txrdy is by tx trigger level and tx fifo empt y (or transmitter empty in auto rs485 control). ? msr is by any of the msr bits, 0, 1, 2 and 3. ? receive xoff/special character is by detec tion of an xoff or special character. ? cts# is when its transmitter toggles the input pin (from low to high) during auto cts flow control. ? rts# is when its receiver toggles the output pin (f rom low to high) during auto rts flow control. ? wake-up indicator: when the uart comes out of sleep mode. 4.4.2 interrupt clearing: ? lsr interrupt is cleared by a read to the lsr register. ? rxrdy is cleared by reading data until fifo falls below the trigger level. ? rxrdy time-out interrupt is cleared by reading rhr. ? txrdy interrupt is cleared by a read to the isr register or writing to thr. ? msr interrupt is cleared by a read to the msr register. ? xoff interrupt is cleared by a read to isr or when xon character(s) is received. ? special character interrupt is cleared by a read to isr or after the next character is received. ? rts# and cts# status change interrupts are cleared by a read to the msr register. ? wake-up indicator is cleared by a read to the isr register.
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 27 ] isr[0]: interrupt status ? logic 0 = an interrupt is pending and the isr contents ma y be used as a pointer to the appropriate interrupt service routine. ? logic 1 = no interrupt pending (default condition) or the device has come out of sleep mode. isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, 3 and 4 (see interrupt source table 9 ). isr[5:4]: interrupt status these bits are enabled when efr bit-4 is set to a logic 1. isr bit-4 indicates that the receiver detected a data match of the xoff character(s). note that once set to a logic 1, the isr bit-4 will stay a logic 1 until a xon character is received. isr bi t-5 indicates that cts# or rts# has changed state. isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disa bled. they are set to a logic 1 when the fifos are enabled. 4.5 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fifos, set the transm it/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr[0]: tx and rx fifo enable ? logic 0 = disable the transmit and receive fifo (default). ? logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no receive fifo reset (default). ? logic 1 = reset the receive fifo pointers and fifo le vel counter logic (the rece ive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. t able 9: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of interrupt l evel b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 1 0 0 0 1 1 0 lsr (receiver line status register) 2 0 0 1 1 0 0 rxrdy (receive data time-out) 3 0 0 0 1 0 0 rxrdy (received data ready) 4 0 0 0 0 1 0 txrdy (transmit ready) 5 0 0 0 0 0 0 msr (modem status register) 6 0 1 0 0 0 0 rxrdy (received xoff or special character) 7 1 0 0 0 0 0 cts#, rts# change of state - 0 0 0 0 0 1 none (default) or wake-up indicator
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 28 fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no transmit fifo reset (default). ? logic 1 = reset the transmit fifo pointers and fifo le vel counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[3]: dma mode select controls the behavior of the txrdy# and rxrdy# pins. see?dma mode? on page 10. ? logic 0 = dma mode disabled (default). ? logic 1 = dma mode enabled. fcr[5:4]: transmit fifo trigger select (logic 0 = default, tx trigger level = one) these 2 bits set the trigger level fo r the transmit fifo inte rrupt. the uart will issue a transmit interrupt when the number of characters in the fifo falls below the select ed trigger level, or when it gets empty in case that the fifo did not get filled over th e trigger level on last re-load. table 10 below shows the sele ctions. efr bit-4 must be set to ?1? before these bits can be accessed. fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1). these 2 bits are used to set the trigger level for the receiver fifo interrupt. table 10 shows the complete selections.. 4.6 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. t able 10: t ransmit and r eceive fifo t rigger l evel s election with auto rts hysteresis fcr b it -7 fcr b it -6 fcr b it -5 fcr bit -4 t ransmit int t rigger l evel r eceive int t rigger l evel a uto rts d e - assert a uto rts r e - assert 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 16 8 24 30 8 16 24 28 16 24 28 28 0 8 16 24 bit-1 bit-0 w ord length 0 0 5 (default) 0 1 6 1 0 7 1 1 8
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 29 lcr[2]: tx and rx stop-bit length select the length of the stop bit is specified by this bit in conjunction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 11 for parity select ion summary below. ? logic 0 = no parity. ? logic 1 = a parity bit is generated duri ng the transmission while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logi c 1, lcr bit-4 selects the even or odd parity format. ? logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format (default). ? logic 1 = even parity is gene rated by forcing an even th e number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format. lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit- 5 selects the forced parity format. ? lcr bit-5 = logic 0, parity is not forced (default). ? lcr bit-5 = logic 1 and lcr bit-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. ? lcr bit-5 = logic 1 and lcr bit-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. lcr[6]: transmit break enable when enabled the break control bit causes a break condition to be transmitted (the tx output is forced to a ?space?, logic 0, state). this co ndition remains until disabled by setting lcr bit-6 to a logic 0. ? logic 0 = no tx break condition (default). ? logic 1 = forces the transmitter output (tx) to a ?space ?, logic 0, for alerting the remote receiver of a line break condition. bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2 t able 11: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, ?1? 1 1 1 forced parity to space, ?0?
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 30 lcr[7]: baud rate divisors enable baud rate generator divisor (dll/dlm) enable. ? logic 0 = data registers are selected (default). ? logic 1 = divisor latch registers are selected if lcr 0xbf . 4.7 modem control register (mcr) or general purpose outputs control - read/write the mcr register is used for contro lling the serial/modem interface signal s or general pur pose inputs/outputs. mcr[0]: dtr# pins the dtr# pin is a modem control output. if the modem interface is not used, this output may be used for general purpose. ? logic 0 = force dtr# output to a logic 1 (default). ? logic 1 = force dtr# output to a logic 0. mcr[1]: rts# pins the rts# pin is a modem control output and may be used for automatic hardware flow control enabled by efr bit-6. if the modem interface is not used, this output may be used for general purpose. ? logic 0 = force rts# output to a logic 1 (default). ? logic 1 = force rts# output to a logic 0. mcr[2]: op1# output op1# is a general purpose output. ? logic 0 = op1# output is at logic 1 (default). ? logic 1 = op1# output is at logic 0 mcr[3]: op2# or irqn enable during pc mode op2# is a general purpose output available during the in tel bus interface mode of operation. in the pc bus mode, it enables the irqn operation. see pc mode section. during intel bus mode operation: ? logic 0 = op2# output is at logic 1 (default). ? logic 1 = op2# output is at logic 0. during pc mode operation: ? logic 0 = disable irqn operation (default). ? logic 1 = enable irqn operation. mcr[4]: internal loopback enable ? logic 0 = disable loopback mode (default). ? logic 1 = enable local loopback mode, see loopback section and figure 14 . mcr[5]: active/three-state interrupt output enable ? logic 0 = enable active or three-state interrupt output (default). ? logic 1 = enable open source interrupt output mode. see table 3 for detailed information.
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 31 mcr[6]: infrared encoder/decoder enable ? logic 0 = enable the standard modem receive an d transmit input/output interface (default). ? logic 1 = enable infrared irda receive and transmit inputs/outputs. the tx/rx output/input are routed to the infrared encoder/decoder. the data input and output levels conform to the irda infrared interface requirement. the infrared tx output is at logic 0 during idle condition. the infrared receive data input polarity is also logic 0, however, it may be inverted when usin g an infrared module that provides inverted signal output. use register xfr bit-1 to invert the receive input signal level going to the infrared decoder. also see xfr bit-0 for half-duplex operation where the receiver can be disabled while transmitting. mcr[7]: clock prescaler select ? logic 0 = divide by one. the input clock from the crystal or external clock is fed directly to the programmable baud rate generator without further modification, i.e., divide by one (default). ? logic 1 = divide by four. the prescaler divides the input clock from the crystal or external clock by four and feeds it to the programmable baud rate generator, hence, data rates become one forth. 4.8 line status register (lsr) - read only this register provides the status of data transfers between the uart and the host. lsr[0]: receive data ready indicator ? logic 0 = no data in receive holding register or rx fifo (default). ? logic 1 = data has been received and is saved in the receive holding register or rx fifo. lsr[1]: receiver overrun flag ? logic 0 = no overrun error (default). ? logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fi fo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. if ier bit-2 is enabled, an interrupt is generated immediately. lsr[2]: receive data parity error flag ? logic 0 = no parity error (default). ? logic 1 = parity error. the receive character in rhr does not have correct parity information and is suspect. this error is associated with the character available for reading in rhr. if ier bit-2 is enabled, an interrupt is generated when the character is available in the rhr (xfr[3] = 0) or when the character is received (xfr[3] = 1). lsr[3]: receive data framing error flag ? logic 0 = no framing error (default). ? logic 1 = framing error. the receive character did not hav e a valid stop bit(s). this error is associated with the character available for reading in rhr. if ie r bit-2 is enabled, an interrupt is generated when the character is available in the rhr (xfr[3] = 0) or when the character is received (xfr[3] = 1). lsr[4]: receive break flag ? logic 0 = no break condition (default). ? logic 1 = the receiver received a break signal (rx was a logic 0 for at least one character frame time). in the fifo mode, only one break character is loaded into t he fifo. the break indication is cleared when lsr is read, but the rx input may still be a logic 0. if ier bit-2 is enabled , an interrupt is generated when the character is available in the rhr (xfr[3] = 0) or when the character is received (xfr[3] = 1).
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 32 lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indicator. the thr bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to th e transmit shift register. the bit is reset to logic 0 concurrently with the data loading to the transmit holding r egister by the host. in the fifo mode this bit is set when the transmit fifo is empty, it is cleared when the transmit fifo contains at least 1 byte. lsr[6]: transmit shift register empty flag this bit is the transmit shift register empty indicator. th is bit is set to a logic 1 whenever the transmitter goes idle. it is set to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to one whenever the transmit fifo and transmit shift register are both empty. lsr[7]: receive fifo data error flag ? logic 0 = no fifo error (default). ? logic 1 = a global indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit clears when there is no more error(s) in the fifo. 4.9 extra feature register (xfr) - write only this register provides additional featur es and controls to the st16c650a uart. xfr [0]: half-duplex infrared mode enable when infrared mode is enabled, mcr bit-6=1, this bit selects the infrared mode to operate in normal full-duplex or half-duplex mode. this half-duplex mode feature is very desirable when the uart does not want to ?see? its own data that may be reflected. ? logic 0 = disable. the receiver is active during data transmission. ? logic 1 = enable half-duplex operation. the infrared receiver is disabled during data transmission. xfr [1]: invert received infrared input signal this bit controls the input polarity of the infrared data. ? logic 0 = infrared data input idles at logic 0 (default). ? logic 1 = infrared data idles at logic 1, pulses low. xfr [2]: auto rs485 enable this bit enables the auto rs485 direction control featur e for half-duplex operation with rs-485 transceiver. the feature should only be enabled when normal rt s# output and auto rts flow control are not used. ? logic 0 = disable the auto rs485 direction control fu nction. this allows normal rts# output or auto rts flow control operation. ? logic 1 = enable the auto rs485 direction functi on. the rts# output will automati cally change its logic state to control the rs-485 transceiver from sending and receiving. see?auto rs485 half-duplex control? on page 18. xfr [3]: lsr bad data interrupt operation when the lsr interrupt is ena bled, ier bit-2=1, this bit selects when the interrupt pin (int ) will report received character error: parity, framing or break. use this fe ature only if application needs immediate knowledge when a bad character is received. ? logic 0 = received data error interrupt (lsr interrupt) will be generated when the bad character is available for reading from the fifo. this is compatib le to industry standard 16c550 operation. ? logic 1 = received data error interrupt (lsr interrup t) is generated immediately upon receipt of the bad character. it will be reset when lsr is read. if user does not read the bad charac ter out, another bad character interrupt is generated when it?s available for reading from the fifo.
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 33 xfr [4]: xon-any enable this bit enables and disables the xon-any function when xon/xoff software flow control is enabled. ? logic 0 = disable the xon-any function. ? logic 1 = enable the xon-any functi on. the receiver will use any received character as an xon character and resume data transmission. xfr [5]: invert auto rs-485 control output when auto rs485 feature is enabled, xfr[2]=1, rts# output automatically changes its logic state to control the rs-485 transceiver. ? logic 0 = during auto rs-485, rts# control output signal to the transceiver is logic 1 for transmit and logic 0 for receive. ? logic 1 = the rts# output control signal to the transceiver is logic 0 for transmit and logic 1 for receive. user must assert rts# for o peration to take effect. xfr [7:6]: reserved 4.10 modem status register (msr) - read only this register provides the current state of the modem interface signals, or othe r peripheral device that the uart is connected. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used as general purpose inputs/outputs when they are not used with modem signals. msr[0]: delta cts# input flag ? logic 0 = no change on cts# input (default). ? logic 1 = the cts# input has changed state since the la st time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[1]: delta dsr# input flag ? logic 0 = no change on dsr# input (default). ? logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[2]: delta ri# input flag ? logic 0 = no change on ri# input (default). ? logic 1 = the ri# input has changed from a logic 0 to a logic 1, ending of the ringi ng signal. a modem status interrupt will be ge nerated if msr in terrupt is enabled (ier bit-3). msr[3]: delta cd# input flag ? logic 0 = no change on cd# input (default). ? logic 1 = indicates that the cd# input has changed st ate since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by auto cts (efr bit-7). auto cts flow contro l allows starting and stopping of local data transmissions based on the modem cts# signal. a logic 1 on the cts# pin will stop uart transmitter as soon as the current character has finished transmission, and a logic 0 will resume data transmission. norma lly msr bit-4 bit is the compliment of the cts# input. however in the loopback mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status dsr# (active high, logical 1). normally this bit is the compliment of the dsr# input. in the loopback mode, this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used.
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 34 msr[6]: ri input status ri# (active high, logical 1). no rmally this bit is the compliment of the ri # input. in the loopback mode this bit is equivalent to bit-2 in the mcr register. the ri# i nput may be used as a general purpose input when the modem interface is not used. msr[7]: cd input status cd# (active high, logical 1). normally this bit is the co mpliment of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# i nput may be used as a general purpose input when the modem interface is not used. 4.11 infrared transmit pulse width co ntrol register (irp w) - write only the irpw register allows the user to program the encoder?s pulse width. this cuts the led on-time, hence, reducing power consumption. irpw [7:0]: pulse width control a 0x00 value (default) will set the pulse width to normal width of 3/16 of the data bit rate. the programmable infrared pulse width can be calcul ated using the following equation: ? infrared pulse width (pw) = crystal clock period x ?n?, where ?n? is the value in irpw from 1 to 255. examples: crystal frequency = 14.7456mhz (clock period of 67.82ns) pw = 67.82 x ?n? or ranges from 67.82ns to 17.29ms caution: never allow pw to exceed the operating data rate bit period, else the encoder stops. 4.12 scratch pad register (spr) this is an 8-bit general purpose register for the user to store temporary data. the content of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle. 4.13 baud rate generator diviso rs (dll and dlm) - read/write the baud rate generator (brg) is a 16-bit counter that generates the data rate for the transmitter. the rate is programmed through registers dll and dlm which are only accessible when lcr bit-7 is set to ?1?. see programmable baud rate generator section for more deta ils. the concatenation of the contents of dlm and dll gives the 16-bit divisor value which is used to calculate the baud rate: ? baud rate = (clock frequency / 16) / divisor also see mcr bit-7 and table 4 . 4.14 device identification register (dvid) - read only this register contains the device id (0x04 for st16c6 50a). prior to reading this register, dll and dlm should be set to 0x00. 4.15 device revision register (drev) - read only this register contains the device revision information. for example, 0x01 means revision a. prior to reading this register, dll and dlm should be set to 0x00. 4.16 enhanced feature register (efr) enhanced features are enabled or disabled using this register. bit 0-3 provide si ngle or dual consecutive character software flow control selection (see table 12 ). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated in to two sequential characters. caution: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting.
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 35 efr[3:0]: software flow control select combinations of software flow control can be selected by programming these bits. efr[4]: enhanced function bits enable enhanced function control bit. this bit enables ier bits 4- 7, isr bits 4-5, fcr bits 4-5, mcr bits 5-7, xfr bits 0-7 and irpw bits 0-7 to be modified. after modifying any enhanced bits, efr bit-4 can be set to a logic 0 to latch the new values. this feature prevents legacy soft ware from altering or overwriting the enhanced functions once set. normally , it is recommended to leave it enabled, logic 1. ? logic 0 = modification disable/latch enhanced features. ie r bits 4-7, isr bits 4-5, fcr bits 4-5, mcr bits 5- 7, xfr bits 0-7 and irpw bits 0-7 are saved to retain the user settings. after a reset, the ier bits 4-7, isr bits 4-5, fcr bits 4-5, mcr bits 5-7, xfr bits 0-7 and irpw bits 0-7 are set to a logic 0 to be compatible with st16c550 mode. (default). ? logic 1 = enables the above-mentioned register bits to be modified by the user. efr[5]: special character detect enable ? logic 0 = special character detect disabled. (default) ? logic 1 = special character detect enabled. the ua rt compares each incomi ng receive character with data in xoff-2 register. if a match ex ists, the received data will be transferr ed to fifo and isr bit-4 will be set to indicate detection of the special character. bit-0 co rresponds with the lsb bit for the receive character. if flow control is set for co mparing xon1, xoff1 (efr [1 :0]=10) then flow control and special character work normally. however, if flow control is set for comparing xon2, xoff 2 (efr[1:0]=01) then flow control works normally, but xoff2 will not go to the fifo, and will ge nerate an xoff interrupt and a special character interrupt. t able 12: s oftware f low c ontrol f unctions efr bit -3 efr bit -2 efr bit -1 efr bit -0 t ransmit and r eceive s oftware f low c ontrol 0 0 0 0 no tx and rx flow control (default and reset) 0 0 x x no transmit flow control 1 0 x x transmit xon1/xoff1 0 1 x x transmit xon2/xoff2 1 1 x x transmit xon1 and xon2/xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1/xoff1 x x 0 1 receiver compares xon2/xoff2 1 0 1 1 transmit xon1/ xoff1, receiver compares xon1 or xon2, xoff1 or xoff2 0 1 1 1 transmit xon2/xoff2, receiver compares xon1 or xon2, xoff1 or xoff2 1 1 1 1 transmit xon1 and xon2/xoff1 and xoff2, receiver compares xon1 and xon2/xoff1 and xoff2 0 0 1 1 no transmit flow control, receiver compares xon1 and xon2/xoff1 and xoff2
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 36 efr[6]: auto rts flow control enable rts# output may be used for hardware flow control by setting efr bit-6 to logic 1. when auto rts is selected, an interrupt will be generated (if ier bit-6 = 1) when the receive fifo is filled to th e programmed trigger level and rts de-a sserts to a logic 1 at the next upper trigge r level. rts# will retu rn to a logic 0 when fifo data falls below the next lower tr igger level. the rts# output must be asserted (logic 0) before the auto rts can take effect. rts# pin will function as a gener al purpose ou tput when hardware flow control is disabled. ? logic 0 = automatic rts flow control is disabled. (default) ? logic 1 = enable automatic rts flow control. efr[7]: auto cts flow control enable automatic cts flow control. ? logic 0 = automatic cts flow control is disabled. (default) ? logic 1 = enable automatic cts flow control. data tr ansmission stops when cts# input de-asserts to logic 1. data transmission re sumes when cts# input returns to a logic 0. 4.17 software flow control registers (xoff1, xoff2, xon1, xon2) - read/write these registers are used as the prog rammable software flow control characters xoff1, xoff2, xon1, and xon2. for more details, see table 5 .
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 37 t able 13: uart reset conditions registers reset state dll bits 7-0 = 0xxx dlm bits 7-0 = 0xxx rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 xfr bits 7-0 = 0x00 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs irpw bits 7-0 = 0x00 spr bits 7-0 = 0xff efr bits 7-0 = 0x00 xon1 bits 7-0 = 0x00 xon2 bits 7-0 = 0x00 xoff1 bits 7-0 = 0x00 xoff2 bits 7-0 = 0x00 i/o signals reset state tx normal = logic 1 infrared = logic 0 rts# logic 1 dtr# logic 1 op1# logic 1 op2# logic 1 txrdy# logic 0 rxrdy# logic 1 int (intel mode) irqa, irqb, irqc (pc mode) logic 0 three-state condition
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 38 test 1: the following inputs should remain steady at vcc or gnd state to minimize sleep current: a0-a2, d0-d7, ior#, iow#, cs# and modem inputs. also, rx input must idle at logic 1 state while in sleep mode. in mixed voltage environments, where the voltage at any of th e inputs of the 650a is lower than its vcc supply voltage, the sleep current will be higher than the maximum values given here. absolute maximum ratings power supply range 7 volts voltage at any pin -0.5 to 7v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw thermal resistance (48-tqfp) theta-ja = 59 o c/w, theta-jc = 16 o c/w thermal resistance (44-plcc) theta-ja = 53 o c/w, theta-jc = 21 o c/w electrical characteristics dc electrical characteristics u nless otherwise noted : ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.90v to 5.5v s ymbol p arameter l imits 3.3v m in m ax l imits 5.0v m in m ax u nits c ondition v ilck clock input low level -0.3 0.6 -0.5 0.6 v v ihck clock input high level 2.4 vcc 3.0 vcc v v il input low voltage -0.3 0.8 -0.5 0.8 v v ih input high voltage (top mark date code of "gc yyww" and older) 2.0 vcc 2.0 vcc v v ih input high voltage (top mark date code of "hc yyww" and newer) 2.0 5.5 2.0 5.5 v v ol output low voltage 0.4 v i ol = 5 ma v ol output low voltage 0.4 v i ol = 4 ma v oh output high voltage 2.4 v i oh = -5 ma v oh output high voltage 2.0 v i oh = -1 ma i il input low leakage current +/-10 +/-10 ua i ih input high leakage current +/-10 +/-10 ua c in input pin capacitance 5 5 pf i cc power supply current 1.3 3.0 ma i sleep sleep current 30 100 ua see test1
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 39 ac electrical characteristics ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.90v to 5.5v, 70 p f l oad where applicable s ymbol p arameter l imits 3.3v m in m ax l imits 5.0v m in m ax u nit clk clock pulse duration 30 20 ns osc crystal frequency 20 24 mhz osc external clock frequency 33 50 mhz t as address setup time (as# tied to gnd) 5 5 ns t ah address hold time (as# tied to gnd) (top mark date code of "hc yyww" and older) 10 10 ns t ah address hold time (as# tied to gnd) (top mark date code of "i2 yyww" and newer) 0 0 ns t cs chip select width 50 40 ns t rd ior# strobe width 50 40 ns t dy read/write cycle delay 40 30 ns t rdv data access time 40 30 ns t dd data disable time 0 15 0 10 ns t wr iow# strobe width 50 40 ns t ds1 data setup time (as# tied to gnd) 20 10 ns t dh1 data hold time (as# tied to gnd) 5 5 ns t asw address strobe width 35 25 ns t as1 address setup time (as# used) 5 5 ns t ah1 address hold time (as# used) 10 10 ns t as2 address setup time (as# used) 5 5 ns t ah2 address hold time (as# used) 10 10 ns t cs1 delay from chip select to as# 5 5 ns t csh delay from as# to chip select 0 0 ns t cs2 delay from as# to chip select 5 5 ns t rd1 delay from as# to read 10 10 ns t rd2 delay from chip select to ior# 10 10 ns t dis delay from ior# to ddis# 15 10 ns t wr1 delay from as# to iow# 10 10 ns
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 40 t ds2 data setup time (as# used) 20 10 ns t dh2 data hold time (as# used) 5 5 ns t as3 address setup time (pc mode) 5 5 ns t rd3 delay from aen# to ior# 10 10 ns t rd4 delay from ior# to aen# 10 10 ns t wr2 delay from aen# to iow# 10 10 ns t wr3 delay from iow# to aen# 10 10 ns t ds3 data setup time (pc mode) 20 10 ns t dh3 data hold time (pc mode) 5 5 ns t wdo delay from iow# to output 50 40 ns t mod delay to set interrupt from modem input 40 35 ns t rsi delay to reset interrupt from ior# 40 35 ns t ssi delay from stop to set interrupt 1 1 bclk t rri delay from ior# to reset interrupt 45 40 ns t si delay from stop to interrupt 45 40 ns t int delay from initial int re set to transmit start 8 24 8 24 bclk t wri delay from iow# to reset interrupt 45 40 ns t ssr delay from stop to set rxrdy# 1 1 bclk t rr delay from ior# to reset rxrdy# 45 40 ns t wt delay from iow# to set txrdy# 45 40 ns t srt delay from center of start to reset txrdy# 8 8 bclk t rst reset pulse width 40 40 ns n baud rate divisor 1 2 16 -1 1 2 16 -1 - bclk baud clock 16x of data rate hz ac electrical characteristics ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.90v to 5.5v, 70 p f l oad where applicable s ymbol p arameter l imits 3.3v m in m ax l imits 5.0v m in m ax u nit
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 41 f igure 15. c lock t iming f igure 16. m odem i nput /o utput t iming osc clk clk external clock iow # iow rts# dtr# cd# cts# dsr# int ior# ior ri# twdo tmod tmod trsi tmod active active change of state change of state active active active change of state change of state change of state active active
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 42 f igure 17. d ata b us r ead t iming in i ntel b us m ode with as# tied to gnd f igure 18. d ata b us w rite t iming in i ntel b us m ode with as# tied to gnd t as t dd t ah t rd t rdv t dy t dd t rdv t ah t as t cs valid address valid address valid data valid data a0- a2 cs2# ior# d0-d7 t cs t rd cs0 cs1 ior note: only one chipselect and one read strobe should be used. t as t dh1 t ah t wr t ds1 t dy t dh1 t ds1 t ah t as t cs valid address valid address valid data valid data a0- a2 cs2# iow# d0-d7 t cs t wr cs1 cs0 iow note: only one chipselect and one write strobe should be used.
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 43 f igure 19. d ata b us r ead t iming in i ntel b us m ode using as# f igure 20. d ata b us w rite t iming in i ntel b us m ode using as# t as1 t dd t ah1 t rd t rdv t dy valid address valid data a0-a2 cs2# ior# d0-d7 t cs cs0 or cs1 ior as# t asw t cs1 t csh t rd1 ddis# t asw valid address t cs t ah2 t csh t dis t rd2 t rd t dis t rdv valid data t dd t as2 t cs2 note: only one chipselect and one read strobe should be used. t as1 t dh2 t ah1 t wr t ds2 t dy valid address valid data a0-a2 cs2# iow# d0-d7 t cs cs0 or cs1 iow as# t asw t cs1 t csh t wr1 t asw valid address t cs t ah2 t csh t wr1 t wr valid data t dh2 t as2 t cs1 t ds2 note: only one chipselect and one write strobe should be used.
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 44 f igure 21. d ata b us r ead t iming in pc m ode f igure 22. d ata b us w rite t iming in pc m ode t as3 t dd t rd4 t rd t rdv t dy t dd t rdv t rd4 t as3 t cs valid address valid address valid data valid data a0-a9 aen# ior# d0-d7 rdtm t cs t rd t rd3 t rd3 t as3 t dh3 t wr3 t wr t ds3 t dy t dh3 t ds3 t wr3 t as3 t cs valid address valid address valid data valid data a0-a9 aen# iow# d0-d7 t cs t wr t wr2 t wr2
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 45 f igure 23. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] f igure 24. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] rx rxrdy# ior# int d0:d7 start bit d0:d7 stop bit d0:d7 t ssr 1 byte in rhr active data ready active data ready active data ready 1 byte in rhr 1 byte in rhr t ssr t ssr rxnfm t rr t rr t rr t ssr t ssr t ssr (reading data out of rhr) tx txrdy# iow# int* d0:d7 start bit d0:d7 stop bit d0:d7 t wt txnonfifo t wt t wt t wri t wri t wri t srt t srt t srt *int is cleared when the isr is read or when data is loaded into the thr. isr is read isr is read isr is read (loading data into thr) (unloading) ier[1] enabled
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 46 f igure 25. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] f igure 26. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] rx rxrdy# ior# int d0:d7 s t ssr rxintdma# rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties first byte is received in rx fifo d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo) rx rxrdy# ior# int d0:d7 s t ssr rxfifodma rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo)
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 47 f igure 27. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] f igure 28. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] tx txrdy# iow# int* txdma# d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri (unloading) (loading data into fifo) last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level data in tx fifo tx fifo empty t wt t srt tx fifo empty t t s t si isr is read ier[1] enabled isr is read *int is cleared when the isr is read or when tx fifo fills up to the trigger level. tx txrdy# iow# int* d0:d7 s txdma d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri t (unloading) (loading data into fifo) last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level at least 1 empty location in fifo t srt tx fifo full t wt t si isr read isr read *int cleared when the isr is read or when tx fifo fills up to trigger level. ier[1] enabled
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 48 package dimensions (48 pin tqfp - 7 x 7 x 1 mm ) note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.039 0.047 1.00 1.20 a 1 0.002 0.006 0.05 0.15 a 2 0.037 0.041 0.95 1.05 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.346 0.362 8.80 9.20 d 1 0.272 0.280 6.90 7.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 0 7 0 7 36 25 24 13 1 1 2 37 48 d d 1 d d 1 b e a 2 a 1 a seating plane l c
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo 49 package dimensions (44 pin plcc) note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.165 0.180 4.19 4.57 a 1 0.090 0.120 2.29 3.05 a 2 0.020 --- 0.51 --- b 0.013 0.021 0.33 0.53 b 1 0.026 0.032 0.66 0.81 c 0.008 0.013 0.19 0.32 d 0.685 0.695 17.40 17.65 d 1 0.650 0.656 16.51 16.66 d 2 0.590 0.630 14.99 16.00 d 3 0.500 typ. 12.70 typ. e 0.050 bsc 1.27 bsc h 1 0.042 0.056 1.07 1.42 h 2 0.042 0.048 1.07 1.22 r 0.025 0.045 0.64 1.14 44 lead plastic leaded chip carrier (plcc) rev. 1.00 1 d d 1 a a 1 d d 1 d 3 b a 2 b 1 e seating plane d 2 244 d 3 c r 45 x h 2 45 x h 1
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 50 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2005 exar corporation datasheet august 2005. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. revision history d ate r evision d escription january 2001 4.20 updated information specific to device revision "fc" and newer: 2.90v to 5.5v operation with 5v tolerant inputs 3.125 mbps dta rate at 5v and 2 mbps at 3.3v auto rs485 half-duplex control output wireless infrared (irda) encoder with programmable pulse width capability and decoder interface description of device id & re vision, irpw and xfr registers december 2001 4.30 updated values in ac electrical characteristics table. january 2004 5.0.0 changed to standard style format. clarified timing diagrams. added device status to ordering information. devices with top mark date code of "i2 yyww" and newer have 0 ns address hold time. devices with top mark date code of "hc yyww" and older do not have this feature. august 2005 5.0.1 removed discontinued 40-pin pdip from ordering information.
xr st16c650a rev. 5.0.1 2.90v to 5.5v uart with 32-byte fifo i table of contents general description........ ................. ................ ................ ............... .............. ........... 1 f eatures ............................................................................................................................... ................... 1 a pplications ............................................................................................................................... .............. 1 f igure 1. b lock d iagram ............................................................................................................................... ...................................... 1 ordering information ............................................................................................................................. 2 f igure 2. i ntel and pc mode p in o ut ............................................................................................................................... .................. 2 pin descriptions ........ ................. ................ ................ ................. ................ .............. 3 1.0 product description ....................................................................................................... ......... 7 2.0 functional descriptions ............................................................................................... 8 2.1 h ost d ata b us i nterface ............................................................................................................... 8 f igure 3. st16c650a i ntel b us i nterconnections .......................................................................................................................... 8 f igure 4. st16c650a pc m ode i nterconnections ........................................................................................................................... 8 2.1.1 pc mode .................................................................................................................. ................................ 9 t able 1: pc m ode i nterface o n - chip a ddress d ecoder and i nterrupt s election . ...................................................................... 9 f igure 5. pc m ode i nterface in an e mbedded a pplication . ............................................................................................................. 9 2.2 5-v olt t olerant i nputs ................................................................................................................ 10 2.3 d evice r eset .............................................................................................................................. .... 10 2.4 d evice i dentification and r evision .............................................................................................. 10 2.5 dma m ode .............................................................................................................................. ........ 10 t able 2: txrdy# and rxrdy# o utputs in fifo and dma m ode .................................................................................................. 10 2.6 i nterrupt .............................................................................................................................. ......... 11 t able 3: i nterrupt o utput (int and irqa) f unctions ................................................................................................................... 11 2.7 c rystal o scillator or e xternal c lock ..................................................................................... 12 f igure 6. t ypical oscillator connections ............................................................................................................................... ....... 12 2.8 p rogrammable b aud r ate g enerator ......................................................................................... 12 f igure 7. b aud r ate g enerator ............................................................................................................................... ....................... 13 t able 4: t ypical data rates with a 14.7456 mh z crystal or external clock .............................................................................. 13 2.9 t ransmitter .............................................................................................................................. ..... 13 2.9.1 transmit holding register (t hr) - write only ............................................................................. ............ 14 2.9.2 transmitter operation in non-fifo mode ................................................................................... ............. 14 f igure 8. t ransmitter o peration in non -fifo m ode ...................................................................................................................... 14 2.9.3 transmitter operation in fifo mode ....................................................................................... ................ 14 f igure 9. t ransmitter o peration in fifo and f low c ontrol m ode ............................................................................................. 14 2.10 r eceiver .............................................................................................................................. ......... 15 2.10.1 receive holding register (rhr) - read-only ...... ........................................................................ ......... 15 f igure 10. r eceiver o peration in non -fifo m ode ......................................................................................................................... 15 f igure 11. r eceiver o peration in fifo and a uto rts f low c ontrol m ode ............................................................................... 16 2.11 a utomatic rts (h ardware ) f low c ontrol .............................................................................. 16 2.12 a uto cts f low c ontrol ............................................................................................................ 16 f igure 12. a uto rts and cts f low c ontrol o peration .............................................................................................................. 17 2.13 a uto x on /x off (s oftware ) f low c ontrol ............................................................................... 17 t able 5: a uto x on /x off (s oftware ) f low c ontrol ....................................................................................................................... 18 2.14 s pecial c haracter d etect ......................................................................................................... 18 2.15 a uto rs485 h alf - duplex c ontrol ........................................................................................... 18 t able 6: rs485 h alf -d uplex c ontrol ............................................................................................................................... .............. 18 2.16 i nfrared m ode ............................................................................................................................. 19 f igure 13. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding ................................................................................. 19 2.17 s leep m ode & w ake - up i ndicator .............................................................................................. 20 2.18 i nternal l oopback ...................................................................................................................... 21 f igure 14. i nternal l oop b ack ............................................................................................................................... .......................... 21 3.0 uart configuration regi sters .................................... ............................................. 22 t able 7: st16c650a uart configuration registers ..................................................................................... ..................... 22 t able 8: uart configuration registers description. s haded bits are enabled when efr b it -4=1. .......................... 23 4.0 internal register descriptions ............................................................................................ .. 24 4.1 r eceive h olding r egister (rhr) - r ead -o nly ............................................................................ 24 4.2 t ransmit h olding r egister (thr) - w rite -o nly ......................................................................... 24
st16c650a xr 2.90v to 5.5v uart with 32-byte fifo rev. 5.0.1 ii 4.3 i nterrupt e nable r egister (ier) - r ead /w rite ........................................................................... 24 4.3.1 ier versus receive fifo inte rrupt mode operation...... .............. .............. .............. .............. ........... ....... 24 4.3.2 ier versus receive/transmit fi fo polled mode operation ................................................................... . 25 4.4 i nterrupt s tatus r egister (isr) - r ead -o nly ............................................................................ 26 4.4.1 interrupt generation: ......... .............. .............. .............. .............. .............. ........... .......... ............................ 26 4.4.2 interrupt clearing:...................................................................................................... ............................... 26 t able 9: i nterrupt s ource and p riority l evel ............................................................................................................................... 27 4.5 fifo c ontrol r egister (fcr) - w rite -o nly ............................................................................... 27 t able 10: t ransmit and r eceive fifo t rigger l evel s election with auto rts hysteresis ....................................................... 28 4.6 l ine c ontrol r egister (lcr) - r ead /w rite ................................................................................. 28 t able 11: p arity selection ............................................................................................................................... ................................. 29 4.7 m odem c ontrol r egister (mcr) or g eneral p urpose o utputs c ontrol - r ead /w rite ........ 30 4.8 l ine s tatus r egister (lsr) - r ead o nly ..................................................................................... 31 4.9 e xtra f eature r egister (xfr) - w rite o nly .............................................................................. 32 4.10 m odem s tatus r egister (msr) - r ead o nly ............................................................................. 33 4.11 i nfrared t ransmit p ulse w idth c ontrol r egister (irpw) - w rite o nly ............................. 34 4.12 s cratch p ad r egister (spr) ...................................................................................................... 34 4.13 b aud r ate g enerator d ivisors (dll and dlm) - r ead /w rite .................................................. 34 4.14 d evice i dentification r egister (dvid) - r ead o nly .................................................................. 34 4.15 d evice r evision r egister (drev) - r ead o nly ......................................................................... 34 4.16 e nhanced f eature r egister (efr) ............................................................................................ 34 t able 12: s oftware f low c ontrol f unctions ............................................................................................................................... 35 4.17 s oftware f low c ontrol r egisters (xoff1, xoff2, xon1, xon2) - r ead /w rite ............... 36 t able 13: uart reset conditions ..................................................................................................... ........................................ 37 electrical characteristics ........ ................ ................ ............... .............. ...........38 dc e lectrical c haracteristics ...........................................................................................................38 ac e lectrical c haracteristics ............................................................................................................39 ta=0 o to 70 o c (-40 o to +85 o c for industrial grade package ), v cc is 2.90v to 5.5v, 70 p f l oad where applicable 39 f igure 15. c lock t iming ............................................................................................................................... ..................................... 41 f igure 16. m odem i nput /o utput t iming ............................................................................................................................... ............. 41 f igure 17. d ata b us r ead t iming in i ntel b us m ode with as# tied to gnd ................................................................................. 42 f igure 18. d ata b us w rite t iming in i ntel b us m ode with as# tied to gnd ............................................................................... 42 f igure 20. d ata b us w rite t iming in i ntel b us m ode using as# ................................................................................................... 43 f igure 19. d ata b us r ead t iming in i ntel b us m ode using as#..................................................................................................... 43 f igure 22. d ata b us w rite t iming in pc m ode ............................................................................................................................... .44 f igure 21. d ata b us r ead t iming in pc m ode ............................................................................................................................... .. 44 f igure 23. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] ................................................................................................... 45 f igure 24. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] ................................................................................................. 45 f igure 25. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ].................................................................................. 46 f igure 26. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ]................................................................................... 46 f igure 27. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] ..................................................................... 47 f igure 28. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] ...................................................................... 47 p ackage d imensions (48 pin tqfp - 7 x 7 x 1 mm )..................................................................................48 p ackage d imensions (44 pin plcc).......................................................................................................49 r evision h istory ............................................................................................................................... .....50 table of contents ............................................................................................................. .................... i

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